1. Field of the Invention
The present invention relates to circuitry for use by interfaces in computer systems; more specifically, the present invention relates to circuitry for generating clock signals of a desired frequency for interfaces.
2. Art Background
Computer systems are generally divided into a group of components. These components are generally driven by a common "clock" or signal line carrying a signal of a predetermined frequency. The phases of the clock signal are used for sequencing logic in integrated circuits, as well as for enabling memory arrays and other components in a computer system. The clock signal is provided to the various components in the computer system and components typically carry out their operation or set of operations during one or more clock cycles.
In the past, it has been quite common for all the components of the computer system to be driven by the same clock reference signal. This has required that computer designers design computer systems around a target operating clock frequency. Systems designed to operate at a single clock frequency are difficult to upgrade with components that operate at different clock frequencies. In order to accomodate faster components while still supporting slower components, modifications are required for the clock generation hardware. Modifying the clocking hardware results in additional expense to upgrade, less design reuse and longer time periods between design and marketing.
In those computer systems where some components operate with faster clock cycles than others, the hardware that propagates the reference clock signal to the components have had to be sensitive to introducing a clock skew. Skew refers to the phase difference between the reference clock and the clock signal seen by each of the components. These offsets may occur due to propagation delays in the circuitry. As clock frequencies increase, the allowable error margin to account for skew decreases. Frequency multiplication is traditionally performed using a simple and well known circuit which utilizes a phase locked loop (PLL). A basic frequency multiplier using a PLL is described in Horowitz & Hill, The Art of Electronics, 2d ed. Cambridge University Press, 1989, P. 647. Such a circuit can generate only whole multiples of the input clock frequency, thereby not accounting for secondary clock frequencies which are not integer multiples of the reference clock.
At the present, when it is desirable to upgrade a computer system to utilize faster components or a faster reference clock signal, it is necessary to replace all the components requiring the previous target clock signal. If a faster CPU is used either all other components must be upgraded or new clock generation circuits must be designed. The two clock domains may also be run asynchronously, so that there is no relation between the fast and slow clock. However, this requires additional clocking crystals which result an increased costs and also necessitates resynchronizing circuitry which yields added costs and performance reduction. The introduction of multiple clock domains introduces further complications that may defeat the purpose of upgrading altogether. Such is the case where a performance critical portion of the system is upgraded to run at a very high frequency but must then be interfaced with another part of the system having a lower frequency.
It would be advantageous, and is therefore an object of the present invention, to develop a programmable interface for components in which a single master clock signal is converted to each component's required clock speed. This can be implemented independent of system configuration.